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author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-06-20 17:26:21 +0300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:19:51 +0000 |
commit | 922c67bd35e9c8542d593d628f28d98521d18f10 (patch) | |
tree | 9526927c105f7c6453e62f0c6c3c4f65966747dd /src/mainboard/intel/dg41wv | |
parent | 12a13e1f30a62513d1ade0cef1d5f815b5ddad65 (diff) |
mb/up/squared/gpio: 1/3 Decode raw register values
Use the intelp2m utility [1] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p apl -file ./up-gpio.h
This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":
CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG
[1] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/dg41wv')
0 files changed, 0 insertions, 0 deletions