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| author | Wim Vervoorn <wvervoorn@eltan.com> | 2020-05-07 12:41:13 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-11 09:30:04 +0000 |
| commit | d6b682cf921b79752810b5df059c54659475a17c (patch) | |
| tree | 0f4a6f1362c3aa5a190078daab1512894caf7ecf /src/mainboard/intel/dg41wv/gpio.c | |
| parent | f5472a10c6fc3f0c452c514c7a23b7046e42ac55 (diff) | |
soc/intel/skylake: Allow setting of PcieRpMaxPayload
Add setting of the MaxPayload for each root port from the device tree.
By default MaxPayload is set to 128 bytes. This change allows changing
to 256 bytes.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/intel/dg41wv/gpio.c')
0 files changed, 0 insertions, 0 deletions