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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 10:04:56 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:28:10 +0000 |
| commit | 1eecb8c814fa05e9902ddcb139a6e8b3a226ffa6 (patch) | |
| tree | 5897829e5767fcf0d7f27c51b355b9027c2e64c8 /src/mainboard/intel/dg41wv/devicetree.cb | |
| parent | 22d6ee8d9cda51d20ca4173593b9574f7dac65ff (diff) | |
nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dg41wv/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/dg41wv/devicetree.cb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 5f945c1c33..9e5c136bc2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x8086 0x5756 |