aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/intel/dg41wv/Makefile.inc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2017-06-01 14:50:07 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-05-26 08:25:50 +0000
commitfbc508fbb84ddbd047a8fde271c3877f032e48d1 (patch)
treeb36ccbc56e9d62a4ff28b076b0611c815ad0d95d /src/mainboard/intel/dg41wv/Makefile.inc
parente3011451cccece7668f95e59dfb6f61c878b7e0a (diff)
mb/intel/dg41wv: Add mainboard
This board was used a test target for the x4x DDR3 raminit patches and has an easy to access DIP8 socket. What is tested and works: * S3 resume * PEG, PCI, USB, SATA * Sound * Ethernet * Native graphic init (textmode and linear fb) on the VGA output * Passing memtest86+ with 2 2Rx8 4G dimms * PS2 Keyboard * Flashing coreboot internally from vendor BIOS. What does not work: * Running dram at 533 MHz (limited at 400MHz currently) Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux 4.10. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dg41wv/Makefile.inc')
-rw-r--r--src/mainboard/intel/dg41wv/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc
new file mode 100644
index 0000000000..f3d7e76263
--- /dev/null
+++ b/src/mainboard/intel/dg41wv/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += cstates.c
+romstage-y += gpio.c