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authorAngel Pons <th3fanbus@gmail.com>2021-01-20 16:43:13 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-12 07:52:01 +0000
commitea573b04d8da056ce41833975cadf58df843c01e (patch)
tree09c471f036fc204d56496f540a329163b2bc1860 /src/mainboard/intel/dcp847ske
parent64c6a746ac78a207703d18b806cb0baa223ebbf5 (diff)
sandybridge MRC boards: Drop channel disable masks
Platform code will overwrite these values anyway, so do not program them in mainboards. Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
-rw-r--r--src/mainboard/intel/dcp847ske/romstage.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index d52ea3c93d..df8112cdbb 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -32,12 +32,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
.gbe_enable = 1,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 2,
- .dimm_channel1_disabled = 2,
.max_ddr3_freq = 1333,
.usb_port_config = {
#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }