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authorAngel Pons <th3fanbus@gmail.com>2021-01-20 01:22:20 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-10 07:29:14 +0000
commitd9e58dca9e72ca2efa62eab832aad606c9c58fcd (patch)
tree565e2a763d0e70c2efcc0ce744599829679a275c /src/mainboard/intel/dcp847ske
parenta2a9e607b1e92f322da25d0ca23ce565eb2b17d7 (diff)
nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
-rw-r--r--src/mainboard/intel/dcp847ske/romstage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index 391d1f23b2..d52ea3c93d 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -14,9 +14,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
+ .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
+ .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
+ .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,