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authorTobias Diedrich <ranma+coreboot@tdiedrich.de>2017-12-03 10:09:28 +0100
committerMartin Roth <martinroth@google.com>2017-12-22 16:45:50 +0000
commit7a9520483aad833cb11fadf3ee12decee8d1e521 (patch)
treecab0d686474b6d1dc219f5d9bc4c01f190c240b2 /src/mainboard/intel/dcp847ske/mainboard.c
parentd7de7bc1ee5d6a0e41ab54a9843448f651ed47e4 (diff)
intel/dcp847ske: Add Intel NUC DCP847SKE
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE Created using autoport and manual edits. mainboard_fill_pei_data copied and adjusted from samsung/lumpy. Tested: - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V). - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V). - SeaBIOS stable payload. - Linux 4.13.14 payload. - Booting into Linux 4.13.14 with Debian/unstable installed on the internal mSATA slot. - Non-native raminit (works). - Native raminit - KVR1333D3S9 doesn't work. - KVR16LS11 only works at 1.5V. - Native VGA init, HDMI port detection with libgfxinit. - Basic ACPI functions (power button event; power-off; reboot). - Suspend to RAM and resume works. - PCIe WLAN in half-minicard slot. - USB device in half-minicard slot. - PCIe device in full-minicard slot. - mSATA device in full-minicard slot. - Fan spins up/down in response to CPU load. Known issues: - Native raminit fails timC calibration with the RAM I have. - Technical Product Specification mentions overcurrent protection for back panel and front panel USB connectors, but I haven't been able to trigger it with either native fw or coreboot (tried up to 2.5A load). Untested: - USB debug port. Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel/dcp847ske/mainboard.c')
-rw-r--r--src/mainboard/intel/dcp847ske/mainboard.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c
new file mode 100644
index 0000000000..5dc4ab6b0f
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/mainboard.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/common/gpio.h>
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_DEBUG, "Memory voltage: %s\n",
+ get_gpio(8) ? "1.35V" : "1.5V");
+ printk(BIOS_DEBUG, "BIOS_CFG jumper: %s\n",
+ get_gpio(22) ? "normal (1-2)" : "setup (2-3)");
+ printk(BIOS_DEBUG, "mSATA: %s\n",
+ get_gpio(35) ? "present" : "absent");
+
+ install_intel_vga_int15_handler(
+ GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};