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authorKeith Hui <buurin@gmail.com>2024-02-05 19:18:43 -0500
committerMartin L Roth <gaumless@gmail.com>2024-06-08 00:19:23 +0000
commita911b758482025d46e132eeb2ed0279b65692075 (patch)
treefb8475ef03a0365132fefb82bc248468ef0a4784 /src/mainboard/intel/dcp847ske/devicetree.cb
parentee126348726b24fbf6e5435bb2cf15417959a8f7 (diff)
mb/*: Remove old USB configurations from SNB/bd82x6x boards
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dcp847ske/devicetree.cb')
-rw-r--r--src/mainboard/intel/dcp847ske/devicetree.cb16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 8b10b6b36c..954f572b31 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -15,22 +15,6 @@ chip northbridge/intel/sandybridge
register "max_mem_clock_mhz" = "666"
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
- register "usb_port_config" = "{
- {1, 0, 0x0040},
- {1, 0, 0x0040},
- {1, 1, 0x0040},
- {1, 1, 0x0040},
- {1, 2, 0x0040},
- {1, 2, 0x0040},
- {1, 3, 0x0040},
- {0, 3, 0x0040},
- {0, 4, 0x0040},
- {0, 4, 0x0040},
- {0, 5, 0x0040},
- {0, 5, 0x0040},
- {0, 6, 0x0040},
- {0, 6, 0x0040}, }"
-
device domain 0 on
device ref host_bridge on end # Host bridge
device ref peg10 off end # PCIe Bridge for discrete graphics