diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 10:03:40 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:28:03 +0000 |
| commit | 22d6ee8d9cda51d20ca4173593b9574f7dac65ff (patch) | |
| tree | 9b672418bce3536132eceff8a288d0ef7340e1ed /src/mainboard/intel/d945gclf/devicetree.cb | |
| parent | 2fb6f68ef09358aa6f2550519e71a1d74702d5ef (diff) | |
nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d945gclf/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/d945gclf/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 669122fb5c..0238e04a48 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/i945 device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_441 device lapic 0 on end end @@ -11,6 +12,7 @@ chip northbridge/intel/i945 register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops subsystemid 0x8086 0x464c inherit device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port |