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| author | Tao Xia <xiatao5@huaqin.corp-partner.google.com> | 2020-11-11 15:32:46 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-11-16 07:15:19 +0000 |
| commit | f3c0a01dc6c4b07af8320f083d9b21e65299e0ed (patch) | |
| tree | bbd7a45ece7b8ae1a903978d7950b386e69c2221 /src/mainboard/intel/d945gclf/Kconfig.name | |
| parent | 17cd905828427d58b67618784cfeefc31d695bdd (diff) | |
mb/google/kukui: Fix LCD sequence T3 fail issue
The T3 that PPVARN_LCD low to LCM_RST_1V8 high is 0.1269ms and
it does not meet the LCD specification that the T3 must be larger
than 5ms. Because there is a delay between PPVARN_LCD_EN and
PPVARN_LCD. An extra 9ms delay should be added on LCM_RST_1V8
in order to meet the specification "ProductSpec_NV105WUM-A51_
V4.3_P2(TLCM).pdf".
BUG=b:172201138
BRANCH=kukui
TEST=The LCD sequence T3 is larger than 5ms when power on.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf/Kconfig.name')
0 files changed, 0 insertions, 0 deletions