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authorElyes Haouas <ehaouas@noos.fr>2022-11-30 07:44:42 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-12-02 14:33:16 +0000
commit87a98b55b2466638587ea44fc7eaa13d93525656 (patch)
treeeca5cd2b63878e4e259fb7f4050137c389ae479f /src/mainboard/intel/d510mo
parent976050113e4f4505579ae3001c9ddf8eeeeaa572 (diff)
nb/intel/pineview: Use {true,false} instead of {0,1}
"use_crt" and "use_lvds" are boolean, so use "true/false". Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d510mo')
-rw-r--r--src/mainboard/intel/d510mo/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index 4b5449fbf9..0464b7489f 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -2,8 +2,8 @@
chip northbridge/intel/pineview # Northbridge
register "gfx.use_spread_spectrum_clock" = "0"
- register "use_crt" = "1"
- register "use_lvds" = "0"
+ register "use_crt" = "true"
+ register "use_lvds" = "false"
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_FCBGA559 # CPU