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authorLin Huang <hl@rock-chips.com>2017-11-02 17:53:30 +0800
committerJulius Werner <jwerner@chromium.org>2017-11-28 19:15:31 +0000
commit45f1b01324ed1712092e80fed7e03fe088452729 (patch)
tree46c995f78dc384dd83bc240db25e3d36795c9371 /src/mainboard/intel/d510mo
parent538b9ef66fc1e24274ae4da2fe9f45531e53a370 (diff)
rockchip/rk3399: mipi: properly configure PHY timing
These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock in order to ensure that the PHY configuration is correct. Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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