diff options
author | Damien Zammit <damien@zamaudio.com> | 2015-05-04 10:41:21 +1000 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-12-02 00:39:03 +0100 |
commit | 74d165b18d749bf959f717b37ea67b84066271d6 (patch) | |
tree | 49426a1ac1cf83be5d957334fcecd1c40695160a /src/mainboard/intel/d510mo/dsdt.asl | |
parent | 149c4c5d0191f1728a66ec986c3eae698cbf87cb (diff) |
mainboard/intel/d510mo: Add Intel D510MO mainboard
Board uses Pineview native raminit
Board boots from grub to linux kernel
VGA needs work, currently headless machine
Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/10074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d510mo/dsdt.asl')
-rw-r--r-- | src/mainboard/intel/d510mo/dsdt.asl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl new file mode 100644 index 0000000000..c1f72f9ac3 --- /dev/null +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/pineview/acpi/pineview.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} |