bd82x6x: Move to common FADT.

Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7200
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

2 files changed, 3 insertions, 171 deletions

diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb
index c499a56c64..42b1535f5b 100644
--- a/src/mainboard/intel/cougar_canyon2/devicetree.cb
+++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb
@@ -43,6 +43,9 @@ chip northbridge/intel/fsp_sandybridge
 
 			register "sata_port_map" = "0x3f"
 
+			register "c2_latency" = "1"
+			register "p_cnt_throttling_supported" = "0"
+
 			device pci 14.0 on end # XHCI
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 on end # Management Engine Interface 2
diff --git a/src/mainboard/intel/cougar_canyon2/fadt.c b/src/mainboard/intel/cougar_canyon2/fadt.c
deleted file mode 100644
index 519167453c..0000000000
--- a/src/mainboard/intel/cougar_canyon2/fadt.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
-	                               0x40) & 0xfffe;
-
-	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(acpi_fadt_t);
-	header->revision = ACPI_FADT_REV_ACPI_3_0;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 1;
-
-	fadt->firmware_ctrl = (u32) facs;
-	fadt->dsdt = (u32) dsdt;
-	fadt->model = 0x00;		/* reserved, should be 0 ACPI 3.0 */
-	fadt->preferred_pm_profile = PM_MOBILE;
-
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x00;
-	fadt->pstate_cnt = 0x00;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x20;
-	fadt->gpe1_blk = 0;
-
-	fadt->pm1_evt_len = 4;		/* 32 bits */
-	fadt->pm1_cnt_len = 2;		/* 32 bit register, 16 bits used */
-	fadt->pm2_cnt_len = 1;		/* 8 bits */
-	fadt->pm_tmr_len = 4;		/* 32 bits */
-	fadt->gpe0_blk_len = 16;	/* 128 bits */
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0x00;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 0;		/* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0;		/* set to 0 if WBINVD is 1 in flags */
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;		/* not supported */
-	fadt->day_alrm = 0x0D;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-	fadt->res2 = 0;			/* reserved, MUST be 0 ACPI 3.0 */
-
-	fadt->flags = ACPI_FADT_WBINVD |
-			ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED |
-			ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_RESET_REGISTER |
-			ACPI_FADT_SEALED_CASE |
-			ACPI_FADT_S4_RTC_WAKE |
-			ACPI_FADT_PLATFORM_CLOCK;
-
-	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->reset_reg.addrl = 0xCF9;
-	fadt->reset_reg.addrh = 0;
-
-	fadt->reset_value = 6;
-	fadt->res3 = 0x00;		/* reserved, MUST be 0 ACPI 3.0 */
-	fadt->res4 = 0x00;		/* reserved, MUST be 0 ACPI 3.0 */
-	fadt->res5 = 0x00;		/* reserved, MUST be 0 ACPI 3.0 */
-
-	fadt->x_firmware_ctl_l = 0x00;	/* set to 0 if firmware_ctrl is used */
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32)dsdt;
-	fadt->x_dsdt_h = 0;
-
-	/* PM1 Status & PM1 Enable */
-	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0;
-
-	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.access_size = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0;
-	fadt->x_pm1b_evt_blk.addrh = 0;
-
-	/* PM1 Control Registers */
-	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x04;
-	fadt->x_pm1a_cnt_blk.addrh = 0;
-
-	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.access_size = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0;
-	fadt->x_pm1b_cnt_blk.addrh = 0;
-
-	/* PM2 Control Registers */
-	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0;
-
-	/* PM1 Timer Register */
-	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x08;
-	fadt->x_pm_tmr_blk.addrh = 0;
-
-	/*  General-Purpose Event Registers */
-	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe0_blk.bit_width = 128;	/* EventStatus + EventEnable */
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
-	fadt->x_gpe0_blk.addrh = 0;
-
-	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.access_size = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0;
-
-	header->checksum =
-	    acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}