diff options
| author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
| commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
| tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/mainboard/intel/cougar_canyon2/devicetree.cb | |
| parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) | |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/cougar_canyon2/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/cougar_canyon2/devicetree.cb | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb deleted file mode 100644 index d7c6aabd4e..0000000000 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ /dev/null @@ -1,70 +0,0 @@ -chip northbridge/intel/fsp_sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort 1 Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DisplayPort 0 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable DVI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end - chip cpu/intel/fsp_model_206ax - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - - chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH - register "sata_port_map" = "0x3f" - - register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" - - device pci 14.0 on end # XHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - # TODO: insert SIO UART and WDT - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end |