mb/intel/coffeelake_rvp: Switch to overridetree setup

This patch moves the common devicetree settings into baseboard and
creates overridetree.cb for each variant. For PCIe root port settings,
SATA, eMMC, I2Cs and GBe, they are in overridetree.

TEST=build an image for each variant

Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 12 insertions, 66 deletions

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index 241ac33345..93b5af9394 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -4,12 +4,6 @@ chip soc/intel/cannonlake
 		device lapic 0 on end
 	end
 
-	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
-	register "ScsEmmcHs400Enabled" = "1"
-	register "HeciEnabled" = "1"
-	register "s0ix_enable" = "1"
-
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
@@ -38,24 +32,6 @@ chip soc/intel/cannonlake
 		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
-
 	register "SataSalpSupport" = "1"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
@@ -74,17 +50,17 @@ chip soc/intel/cannonlake
 	register "PcieRpEnable[2]" = "1"
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
 	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
+	register "PcieRpEnable[9]" = "0"
+	register "PcieRpEnable[10]" = "0"
+	register "PcieRpEnable[11]" = "0"
+	register "PcieRpEnable[12]" = "0"
+	register "PcieRpEnable[13]" = "0"
+	register "PcieRpEnable[14]" = "0"
+	register "PcieRpEnable[15]" = "0"
 
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
@@ -100,43 +76,26 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[4]" = "4"
 	register "PcieClkSrcClkReq[5]" = "5"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPP_G5"
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
 		chip drivers/intel/wifi
 			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
 		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
+        device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on  end # SATA
 		device pci 19.0 on  end # I2C #4
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
 		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+        device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
@@ -148,20 +107,7 @@ chip soc/intel/cannonlake
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 on  end # GbE
 	end
 end