diff options
author | Nico Huber <nico.huber@secunet.com> | 2019-10-02 16:02:06 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2020-08-23 09:57:02 +0000 |
commit | 119ace0908b66b718c4b581423309648b10e4bf7 (patch) | |
tree | b9ed4510a9081065c35af99a06446a74b3db82c1 /src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb | |
parent | 2b9035ed6e51fe835b85dd626e655e1d3901e7ea (diff) |
soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb')
-rw-r--r-- | src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index c5c291df9f..f48c9b49a8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -84,12 +84,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 |