diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2018-08-07 12:06:23 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-14 09:53:09 +0000 |
| commit | dfc9917080a9175fef2c40288c586ff9dd5861f3 (patch) | |
| tree | 4ec7c50b7c3f376ea8884a792212e6f3cf22ad08 /src/mainboard/intel/coffeelake_rvp/dsdt.asl | |
| parent | 8bd25abc051d039dd05ab3c848fc8fae1eb1c736 (diff) | |
mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP
Add support for new board coffeelake RVP.
This patch is a copy patch and copies entire coffeelake_rvp folder from
cannonlake_rvp.
Changes done on top of copy:
1. Change copyright year from 2017 to 2018
2. Rename Cannonlake to Coffelake whenever applicable
3. Update entries in Kconfig and Kconfig.name
4. Rename variant directories to match coffeelake boards
Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/dsdt.asl | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl new file mode 100644 index 0000000000..37a1725c1e --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/cannonlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + + // Chipset specific sleep states + #include <soc/intel/cannonlake/acpi/sleepstates.asl> + +} |