diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-20 12:12:12 -0700 |
|---|---|---|
| committer | Andrey Petrov <anpetrov@fb.com> | 2020-03-26 18:14:46 +0000 |
| commit | 1b325dd971c84d75aa5a53405c11e0ad8f2517b9 (patch) | |
| tree | eb26b8a0d5f5d2895c872ec5c034c90a0159aa92 /src/mainboard/intel/cedarisland_crb/devicetree.cb | |
| parent | 7b42bba3cf287e13eff6b86326f55ef6bf6ff6e0 (diff) | |
mb/intel/cedarisland_crb: Add Cedar Island CRB
Just a minimal set of board files needed to get it to boot
in 1 CPU mode.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/cedarisland_crb/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/cedarisland_crb/devicetree.cb | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb new file mode 100644 index 0000000000..6eb9557484 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -0,0 +1,54 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + end + + end +end |