diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-20 12:12:12 -0700 |
|---|---|---|
| committer | Andrey Petrov <anpetrov@fb.com> | 2020-03-26 18:14:46 +0000 |
| commit | 1b325dd971c84d75aa5a53405c11e0ad8f2517b9 (patch) | |
| tree | eb26b8a0d5f5d2895c872ec5c034c90a0159aa92 /src/mainboard/intel/cedarisland_crb/bootblock.c | |
| parent | 7b42bba3cf287e13eff6b86326f55ef6bf6ff6e0 (diff) | |
mb/intel/cedarisland_crb: Add Cedar Island CRB
Just a minimal set of board files needed to get it to boot
in 1 CPU mode.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/cedarisland_crb/bootblock.c')
| -rw-r--r-- | src/mainboard/intel/cedarisland_crb/bootblock.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c new file mode 100644 index 0000000000..ea82ecc73f --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +void bootblock_mainboard_early_init(void) +{ + /* Enable COM1 only */ + pcr_write32(PID_DMI, 0x2770, 0); + pcr_write32(PID_DMI, 0x2774, 1); + + /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} |