diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-24 17:35:55 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 18:24:47 +0000 |
| commit | 39648bb54b2bdeda3bc5a1bd63b8b5f60478f2f7 (patch) | |
| tree | 69f824d213a50f9d14abbebdae24939ce482612e /src/mainboard/intel/cannonlake_rvp | |
| parent | 9027e1ba2f23eb6b418f60f133da1730b7d989d3 (diff) | |
mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetree
Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb
Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e71f15b8cf..a3c4c80d14 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -4,6 +4,11 @@ chip soc/intel/cannonlake device lapic 0 on end end + # FSP configuration + register "SaGv" = "3" + register "FspSkipMpInit" = "1" + register "SmbusEnable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index e71f15b8cf..a3c4c80d14 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -4,6 +4,11 @@ chip soc/intel/cannonlake device lapic 0 on end end + # FSP configuration + register "SaGv" = "3" + register "FspSkipMpInit" = "1" + register "SmbusEnable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |