diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-08 18:16:13 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-26 21:37:14 +0000 |
| commit | c319bab3cd416d85330774f9974b41fcb49075a7 (patch) | |
| tree | 7533dac79d57499e552393695b5c751a2986eb5c /src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | |
| parent | 735779cc9aa9d6b02fadbdfc0a50fb087cce7731 (diff) | |
intel/cannonlake_rvp: Split RVP boards and SPD
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb new file mode 100644 index 0000000000..c7001a4118 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + end +end |