summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/bayleybay_fsp
diff options
context:
space:
mode:
authorIsaac Christensen <isaac.christensen@se-eng.com>2014-09-24 14:59:32 -0600
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-09-25 23:24:03 +0200
commit81f90c58d2eacf8ee2baf2334fd38bbfa0ef7274 (patch)
tree17d76874340eb3dc6b2b8a2d4b6b236e4fc00666 /src/mainboard/intel/bayleybay_fsp
parentd2f3aa91e0096b087214ee5fc368fa0091d6c52c (diff)
x86/mtrr: Enable MTRR's before enabling caching
Fix up the following commit by enabling the MTRR's before enabling caching. 7756fe7 x86: Minimize work done with the caches disabled in mtrr functions. Also fix two typos in comments. Change-Id: If751b815f9dab781fc38c898cf692f0940c57695 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6969 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel/bayleybay_fsp')
0 files changed, 0 insertions, 0 deletions