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authorMaximilian Brune <maximilian.brune@9elements.com>2024-03-05 21:48:19 +0100
committerMaximilian Brune <maximilian.brune@9elements.com>2024-11-28 13:59:34 +0000
commit0b617c930082d00595a2d7427bc8ce7af6a9f9e9 (patch)
tree718f85be4464b1a4987e4d4c89428d2454e3b00a /src/mainboard/intel/baskingridge/dsdt.asl
parent6c063250b55eb9d7bc96615557fa731474f287fe (diff)
arch/riscv: Refactor SMP code
Currently only a fixed number of harts/cores can be detected. This patch adds a Kconfig option which allows to detect the number of harts at runtime if a SOC or mainboard has a scheme to do so. As part of that patch SMP logic has been mostly moved to smp_resume, since it is easier to debug issues at the time smp_resume is called than it is at smp_pause, since the serial is usually not present at the time of the first smp_pause call. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/mainboard/intel/baskingridge/dsdt.asl')
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