diff options
| author | Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> | 2024-09-02 13:39:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-04 04:38:51 +0000 |
| commit | 174755f55528188ec69efe2836944c6c28e5a976 (patch) | |
| tree | 4bee983ee72be51edd09a23c7d3f395f06eb5cd1 /src/mainboard/intel/baskingridge/chromeos.c | |
| parent | 2e1b7d3a151f37f90ecfc22bbe0236e1a6c918bd (diff) | |
soc/intel/common/block: Include register offsets for POWER_CTL
Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.
Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/mainboard/intel/baskingridge/chromeos.c')
0 files changed, 0 insertions, 0 deletions