diff options
| author | Martin Roth <gaumless@gmail.com> | 2017-04-02 21:13:29 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-02 18:32:10 +0200 |
| commit | 41807626e2eeae3077e5c366c2a7810f7ebba7f2 (patch) | |
| tree | bad206813bf2b7333a66c03bf7b4ac080d33aae9 /src/mainboard/intel/bakersport_fsp/Kconfig | |
| parent | cfbb815efdfbc8c783a6ac631402ab178ee6cb2e (diff) | |
intel/bakersport_fsp: Move into bayleybay_fsp as a variant
The separate directory was the old way of handling variant boards.
Update bakersport_fsp to the new method. All of the other pieces
were already moved into bayleybay_fsp.
Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/intel/bakersport_fsp/Kconfig')
| -rw-r--r-- | src/mainboard/intel/bakersport_fsp/Kconfig | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig deleted file mode 100644 index cc11790cb1..0000000000 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_BAKERSPORT_FSP - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_2048 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select TSC_MONOTONIC_TIMER - -config MAINBOARD_DIR - string - default "intel/bayleybay_fsp" - -config MAINBOARD_PART_NUMBER - string - default "Bakersport CRB (FSP)" - -config MAX_CPUS - int - default 16 - -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - -config FSP_FILE - string - default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP - -config CBFS_SIZE - hex - default 0x00200000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config VIRTUAL_ROM_SIZE - hex - depends on ENABLE_FSP_FAST_BOOT - default 0x800000 - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config VGA_BIOS - bool - default y if FSP_PACKAGE_DEFAULT - -endif # BOARD_INTEL_BAKERSPORT_FSP |