diff options
| author | Zhao, Lijian <lijian.zhao@intel.com> | 2016-03-14 14:19:22 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-20 18:51:18 +0200 |
| commit | d8d42c2f5f61c298d20500dd6f557f336b7e4972 (patch) | |
| tree | 3180eeb0c440e9636ee8856148d7c7289620cab1 /src/mainboard/intel/amenia/devicetree.cb | |
| parent | d68a13a602883d7e5a52ceb9062d71f363855695 (diff) | |
mainboard/amenia: add the inital files for amenia board
Add amenia board files
Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/amenia/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb new file mode 100644 index 0000000000..c54e838826 --- /dev/null +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -0,0 +1,52 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "3" # wifi/bt + register "pcie_rp2_clkreq_pin" = "0" # SSD + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end |