diff options
| author | Divya Sasidharan <divya.s.sasidharan@intel.com> | 2016-02-08 09:45:37 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:13:54 +0200 |
| commit | cbf1a0fec8b84dc936a35428b835501ad0f46a30 (patch) | |
| tree | ba9fc31f4fe0b4b77885a9b35778f8324bb8b68e /src/mainboard/intel/amenia/devicetree.cb | |
| parent | 4520c5e757cf280b7029a99adff60baed52493ce (diff) | |
mainboard/amenia: Enable Chrome EC Interface/Keyboard
Enabled LPC channel between host and EC.
Superio.asl will enable proper probing of onboard keyboard.
Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/14468
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/amenia/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838826..46dae8e618 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,15 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # EC host command range is in 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + register "gen3_dec" = "0x0" + register "gen4_dec" = "0x0" + + # EC also needs 0x200,0x204, 0x60/0x64, 0x62/0x66 + register "lpc_dec" = "0xd00" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |