diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-06-10 19:36:49 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-12 20:38:56 +0200 |
| commit | 6e5c5a15bc9fe709943598ede0eb52f9766cbb02 (patch) | |
| tree | 13f077c46160490697b9882d36fb5c29951d8516 /src/mainboard/intel/amenia/devicetree.cb | |
| parent | 7f149c7bb4744459c775c32c71fe222c792cea19 (diff) | |
intel/amenia: Add GPE routing settings
This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.
BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
and see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupt
Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/amenia/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 7045f59b5d..3b25b2b00a 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -18,6 +18,15 @@ chip soc/intel/apollolake # LPSS S0ix Enable register "lpss_s0ix_enable" = "1" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |