diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-01 11:44:09 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-02 12:36:25 +0000 |
| commit | db925aaf38dfc10de74c80cb1e43a7058fa8811a (patch) | |
| tree | f811185dee4aeb9aab4db00f87d1ff6c459788c7 /src/mainboard/intel/adlrvp | |
| parent | 734a777d94b2f4b74cb635e6159f1440195642e9 (diff) | |
soc/intel/alderlake: Add Kconfigs for all PCH types
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Kconfig | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 2b78515776..657568502d 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -14,7 +14,6 @@ config BOARD_INTEL_ADLRVP_COMMON select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -23,11 +22,13 @@ config BOARD_INTEL_ADLRVP_P select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_P config BOARD_INTEL_ADLRVP_P_EXT_EC select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_INTEL_PMC select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_ALDERLAKE_PCH_P config BOARD_INTEL_ADLRVP_P_MCHP select BOARD_INTEL_ADLRVP_COMMON @@ -36,7 +37,7 @@ config BOARD_INTEL_ADLRVP_P_MCHP select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select INTEL_LPSS_UART_FOR_CONSOLE - select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ALDERLAKE_PCH_P config BOARD_INTEL_ADLRVP_M select BOARD_INTEL_ADLRVP_COMMON |