diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-08-31 10:41:31 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-09-11 01:40:20 +0000 |
| commit | 83481eb0a30ab69b9b010801fc31812174d3d8bc (patch) | |
| tree | b5c685193484088690b461f386fd43117d2dc6d2 /src/mainboard/intel/adlrvp | |
| parent | 8dfef963fdf0c9362bb8b6712e1e93c75a1db65c (diff) | |
tree: use boolean for hybrid_storage_mode
Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 95b006e2f6..a6bad136b6 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,7 +83,7 @@ chip soc/intel/alderlake }" # Hybrid storage mode - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 0b3a3efea0..922b673ce2 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -76,7 +76,7 @@ chip soc/intel/alderlake }" # Hybrid storage mode - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ |