diff options
| author | Reka Norman <rekanorman@google.com> | 2021-11-08 14:53:19 +1100 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-11-09 19:19:51 +0000 |
| commit | 6d27905e039fcf8671f6b761665cb35fb148548f (patch) | |
| tree | ce37382a7f01ee37954efdf07143f9a94c6aad52 /src/mainboard/intel/adlrvp | |
| parent | ba2b1139f1c3479bf7886bb3382216b1e76ad881 (diff) | |
mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.
BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.fmd | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 84adad9ba5..53469de9c2 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -15,7 +15,7 @@ FLASH 32M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 4032K + ME_RW_A(CBFS) 3520K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -39,7 +39,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 4032K + ME_RW_B(CBFS) 3520K } # Make WP_RO region align with SPI vendor # memory protected range specification. |