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authorZhuohao Lee <zhuohao@chromium.org>2022-01-20 21:30:12 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-02-25 20:45:49 +0000
commit09f3b6cf21d735b115d25bf081240979dccd0afc (patch)
tree5779523a9039598bcb4a6893d7b06bc09f1e72cf /src/mainboard/intel/adlrvp
parent9f091608b29526246cb02e79e8b4e8b286824509 (diff)
mb, soc: change mainboard_memory_init_params prototype
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 56bd0cd1b6..a0453efd5f 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -42,8 +42,9 @@ static void configure_external_clksrc(FSP_M_CONFIG *m_cfg)
m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER;
}
-void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
{
+ FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
const struct mb_cfg *mem_config = variant_memory_params();
int board_id = get_board_id();
const bool half_populated = false;