diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-11-03 17:54:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-05 15:39:54 +0000 |
| commit | be7692a20cf323bb257de480957bba12428a973a (patch) | |
| tree | 92322cfa866e701637d90abd8255c6bf0e830f14 /src/mainboard/intel/adlrvp | |
| parent | d16d00b71ae8f1bd679272753144002ada4f63f6 (diff) | |
mb/google,intel: Fix indirect include bootmode.h
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/ramstage.c | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 244b942682..85807a1181 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index f93b361267..93f1aa3a25 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <soc/romstage.h> #include "board_id.h" diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 136fa455df..22902bd48b 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -8,6 +8,7 @@ #include <soc/gpio_soc_defs.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <string.h> #include <drivers/intel/dptf/chip.h> #include "board_id.h" #include <intelblocks/power_limit.h> |