diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-01-09 16:17:45 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-01-10 17:49:19 +0000 |
| commit | 85144d9002d6a712ce793b87e739f613080fcc4a (patch) | |
| tree | 82082476922ab16e0b5d99e1f9ea54146fa2fb0a /src/mainboard/intel/adlrvp | |
| parent | 9a1b720b1f9ea5e589c3e93d16e9a161683f2a4d (diff) | |
soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 12cd47561a..51b781c619 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,39 +40,44 @@ chip soc/intel/alderlake register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 2 - register "PcieRpEnable[4]" = "1" + register "PchPcieRpEnable[4]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcUsage[2]" = "0x4" register "PcieRpClkReqDetect[4]" = "1" # Enable PCH PCIE RP 6 using CLK 5 - register "PcieRpEnable[5]" = "1" + register "PchPcieRpEnable[5]" = "1" register "PcieClkSrcClkReq[5]" = "5" register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" # Enable PCH PCIE RP 8 using CLK 6 - register "PcieRpEnable[7]" = "1" + register "PchPcieRpEnable[7]" = "1" register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6 register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK register "PcieRpClkReqDetect[6]" = "1" # Enable PCH PCIE RP 9 using CLK 1 - register "PcieRpEnable[8]" = "1" + register "PchPcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" # Enable PCH PCIE RP 11 for optane - register "PcieRpEnable[10]" = "1" + register "PchPcieRpEnable[10]" = "1" # Hybrid storage mode register "HybridStorageMode" = "1" - # Enable CPU PCIE RP 1 using PEG CLK 0 + # Enable CPU PCIE RP 1 using CLK 0 + register "CpuPcieRpEnable[0]" = "1" register "PcieClkSrcUsage[0]" = "0x40" - # Enable PCU PCIE PEG Slot 1 and 2 + # Enable CPU PCIE RP 2 using CLK 3 + register "CpuPcieRpEnable[1]" = "1" register "PcieClkSrcUsage[3]" = "0x41" + + # Enable CPU PCIE RP 3 using CLK 4 + register "CpuPcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "0x42" # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below @@ -177,10 +182,12 @@ chip soc/intel/alderlake device domain 0 on device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PEG10 device pci 02.0 on end # Graphics device pci 04.0 on end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 + device pci 06.2 on end # PEG62 device pci 07.0 on end # TBT_PCIe0 device pci 07.1 on end # TBT_PCIe1 device pci 07.2 on end # TBT_PCIe2 |