mb/intel/adlrvp: Add ADL-P romstage mainboard code

List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD

TEST=Able to build and boot ADL-P RVP till ramstage early

Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

4 files changed, 104 insertions, 8 deletions

diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
index 9b21a1b5a4..8c0572163b 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
@@ -1,3 +1,5 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 bootblock-y += early_gpio.c
+
+romstage-y += memory.c
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index e16de65848..a6b0039d0e 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -11,6 +11,36 @@ chip soc/intel/alderlake
 	register "gen3_dec" = "0x00fc0901"
 	register "gen4_dec" = "0x000c0081"
 
+	register "PrmrrSize" = "0"
+
+	# Enable PCH PCIE RP 5 using CLK 2
+	register "PcieRpEnable[4]" = "1"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcUsage[2]" = "0x4"
+	register "PcieRpClkReqDetect[4]" = "1"
+
+	# Enable PCH PCIE RP 6 using CLK 5
+	register "PcieRpEnable[5]" = "1"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcUsage[5]" = "0x5"
+	register "PcieRpClkReqDetect[5]" = "1"
+
+	# Enable PCH PCIE RP 9 using CLK 1
+	register "PcieRpEnable[8]" = "1"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcUsage[1]" = "0x8"
+	register "PcieRpClkReqDetect[8]" = "1"
+
+	# Enable CPU PCIE RP 1 using PEG CLK 0
+	register "PcieClkSrcUsage[0]" = "0x40"
+
+	# Enable PCU PCIE PEG Slot 1 and 2
+	register "PcieClkSrcUsage[3]" = "0x41"
+	register "PcieClkSrcUsage[4]" = "0x42"
+
+	# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
+	register "PcieClkSrcUsage[6]" = "0xff"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Graphics
@@ -79,17 +109,17 @@ chip soc/intel/alderlake
 		device pci 19.1 on  end # I2C5
 		device pci 19.2 on  end # UART2
 		device pci 1c.0 on  end # RP1
-		device pci 1c.1 on  end # RP2
-		device pci 1c.2 on  end # RP3
-		device pci 1c.3 on  end # RP4
+		device pci 1c.1 off end # RP2
+		device pci 1c.2 off end # RP3
+		device pci 1c.3 off end # RP4
 		device pci 1c.4 on  end # RP5
 		device pci 1c.5 on  end # RP6
-		device pci 1c.6 on  end # RP7
-		device pci 1c.7 on  end # RP8
+		device pci 1c.6 off end # RP7
+		device pci 1c.7 off end # RP8
 		device pci 1d.0 on  end # RP9
-		device pci 1d.1 on  end # RP10
-		device pci 1d.2 on  end # RP11
-		device pci 1d.3 on  end # RP12
+		device pci 1d.1 off end # RP10
+		device pci 1d.2 off end # RP11
+		device pci 1d.3 off end # RP12
 		device pci 1e.0 off end # UART0
 		device pci 1e.1 off end # UART1
 		device pci 1e.2 off end # GSPI0
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
new file mode 100644
index 0000000000..f8b366049f
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include "../../board_id.h"
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mem_config = {
+	/* DQ byte map */
+	.dq_map = {
+	{   0,  2,   3,  1,   6,   7,   5,   4,    /* Byte 0 */
+	   10,  8,  11,  9,  14,  12,  13,  15 },  /* Byte 1 */
+	{  12,  8,  14, 10,  11,  13,  15,   9,    /* Byte 2 */
+	    5,  0,   7,  3,   6,   2,   1,   4 },  /* Byte 3 */
+	{   3,  0,   2,  1,   6,   5,   4,   7,    /* Byte 4 */
+	   12, 13,  14, 15,  10,   9,   8,  11 },  /* Byte 5 */
+	{   2,  6,   7,  1,   3,   4,   0,   5,    /* Byte 6 */
+	    9, 13,   8, 15,  14,  11,  12,  10 },  /* Byte 7 */
+	{   3,  0,   1,  2,   7,   4,   6,   5,    /* Byte 0 */
+	   10,  8,  11,  9,  14,  13,  12,  15 },  /* Byte 1 */
+	{  10, 12,  14,  8,   9,  13,  15,  11,    /* Byte 2 */
+	    3,  7,   6,  2,   0,   4,   5,  1 },   /* Byte 3 */
+	{  12, 15,  14, 13,   9,  10,  11,  8,     /* Byte 4 */
+	    7,  4,   6,  5,   0,   1,   3,  2 },   /* Byte 5 */
+	{   0,  2,   4,  3,   1,   6,   7,  5,     /* Byte 6 */
+	   13,  9,  10, 11,   8,  12,  14, 15 },   /* Byte 7 */
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+	/* Ch 0     1         2         3  */
+	{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 },
+	{ 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }
+	},
+
+	/* Baseboard uses only 100ohm Rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	/*
+	 * Baseboard Rcomp target values.
+	 */
+	.rcomp_targets = {40, 30, 33, 33, 30},
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &mem_config;
+}
diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
index 7a8f444fee..5288b6f832 100644
--- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
@@ -4,13 +4,25 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
+#include <soc/meminit.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+enum adl_boardid {
+	/* ADL-P LPDDR4 RVPs */
+	ADL_P_LP4_1 = 0x10,
+	ADL_P_LP4_2 = 0x11,
+	/* ADL-P DDR4 RVPs */
+	ADL_P_DDR4_1 = 0x14,
+	ADL_P_DDR4_2 = 0x3F,
+};
+
 /* The next set of functions return the gpio table and fill in the number of
  * entries for each table. */
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
 void variant_configure_early_gpio_pads(void);
 
+size_t variant_memory_sku(void);
+const struct mb_cfg *variant_memory_params(void);
 #endif /*__BASEBOARD_VARIANTS_H__ */