diff options
| author | Cliff Huang <cliff.huang@intel.corp-partner.google.com> | 2022-04-11 18:49:57 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-16 00:00:03 +0000 |
| commit | 82b7d0cf8c426b98ac8a737531f053585f7d4a58 (patch) | |
| tree | 64579fee1a33e7c599e6cc1275bd514bd3b50752 /src/mainboard/intel/adlrvp/variants | |
| parent | ca741055e6b63b6722ad9837fa5360fa6b5b3e5b (diff) | |
mb/intel/adlrvp: Add 5G WWAN ACPI support for ADL-P RVP
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.
PCIe root port: 6 (1 based)
clock source & request: 5 (0 based)
GPIOs:
WWAN_PERST_N: GPPC_C5
WWAN_RST_N: GPPC_F14
WWAN_FCP_OFF_N: GPPC_F15
WWAN_WAKE_N: GPPC_D18
WWAN_PWREN: GPPC_F21
WWAN_DISABLE_N: GPPC_D15
CLKREQ5_WWAN_N: GPPC_H23
TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3
are generated under the root port.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I10902245e3a5e05cd2af9030394933e936c25396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63941
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/variants')
| -rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index de5471cf65..2eea1e4583 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -57,5 +57,32 @@ chip soc/intel/alderlake end end end + device ref pcie_rp6 on + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C5)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "5" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on + end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F15)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F14)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C5)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "add_acpi_dma_property" = "true" + use rp6_rtd3 as rtd3dev + device generic 0 on + end + end + end end end |