diff options
| author | Tracy Wu <tracy.wu@intel.com> | 2022-01-13 21:53:02 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-17 15:52:33 +0000 |
| commit | ec877d633d0db3b40c28d2ef198313ab688cd3d4 (patch) | |
| tree | 7e2d5f794e8a6f4304b9e25dc9bc0c168a27f283 /src/mainboard/intel/adlrvp/devicetree.cb | |
| parent | c89be7ae425a9a37a2d3be050d607a8dd76147fa (diff) | |
mb/google/brya/variants/*: Add cpu pcie rp flags
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 2c45e85e34..8f60e42970 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -81,18 +81,21 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable CPU PCIE RP 2 using CLK 3 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_req = 3, .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_req = 4, .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" register "SataSalpSupport" = "1" |