diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-05-19 09:42:23 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-08-27 04:36:33 +0000 |
| commit | c398a204b40f6a9ccb06cb9b6af67ad528638a05 (patch) | |
| tree | 9ca0a196cfeb75d2d28ce74c42270c8b46896d49 /src/mainboard/intel/adlrvp/devicetree.cb | |
| parent | 1d19432e1e50dc507af2759bf83c74d5c32c6e4c (diff) | |
mb/intel/adlrvp: Enable SaGv support
BUG=b:187446498
TEST=Boot and verify memory trains at all the SaGv points through FSP
debug logs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index c9d7da6cbc..c5207f205f 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/alderlake # Enable CNVi BT register "CnviBtCore" = "true" + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 |