diff options
| author | Cliff Huang <cliff.huang@intel.corp-partner.google.com> | 2022-04-28 18:38:44 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 13:13:03 +0000 |
| commit | 6c6be42c9fe1e03550aae6bf33bd8357021831b9 (patch) | |
| tree | 997f07ab1802cb36d21664df4d94b8b5548239b7 /src/mainboard/intel/adlrvp/devicetree.cb | |
| parent | edbbabcbe7d3f3dd4e636ab7f363b22687c0399e (diff) | |
mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVP
Use clock src and clock req to 7 for x4 slot.
Remove free running clock setting for clock 6.
Configure gpio for source clock OEB native function going to x4 slot.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check
the device.
ex:
58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01)
NOTE: The bus number varies.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 8847d88f93..df4ac6046a 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -52,12 +52,14 @@ chip soc/intel/alderlake .flags = PCIE_RP_CLK_REQ_DETECT, }" - # Enable PCH PCIE RP 8 using free running CLK (0x80) - # Clock source is shared with LAN and hence marked as free running. + # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7 register "pch_pcie_rp[PCH_RP(8)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, }" - register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" # Enable PCH PCIE RP 9 using CLK 1 register "pch_pcie_rp[PCH_RP(9)]" = "{ |