diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-05 21:04:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-08 04:10:37 +0000 |
| commit | efc40090f5711ea53df086606bf20ea8f476f871 (patch) | |
| tree | 5aa8ac61484260a5544ebb88d60d093671dac34f /src/mainboard/intel/adlrvp/chromeos.fmd | |
| parent | 58222d156a2609bdc3e78222c9bf03a0697d6c2a (diff) | |
mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes:
1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig
2. Add minimum code to make ADL-P RVP build successfully
3. Mainly bootblock and verstage code added to reach till verstage
4. Add support for 2 mainboards as ADL-P board with default EC (Windows
SKU) and Chrome EC (Chrome SKU)
5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/chromeos.fmd')
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.fmd | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000000..48666629db --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 32M { + SI_ALL 0x1081000 { + SI_DESC 0x1000 + SI_EC 0x80000 + SI_ME + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A 0x368000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x357fc0 + RW_FWID_A 0x40 + } + RW_SECTION_B 0x368000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x357fc0 + RW_FWID_B 0x40 + } + RW_MISC 0x30000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 + } + RW_VPD(PRESERVE) 0x2000 + RW_NVRAM(PRESERVE) 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS) 0x100000 + WP_RO { + RO_VPD(PRESERVE) 0x4000 + RO_SECTION { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0x3000 + COREBOOT(CBFS) + } + } + } +} |