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| author | Subrata Banik <subrata.banik@intel.com> | 2020-11-27 00:46:18 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-01 07:52:26 +0000 |
| commit | 840679d2c1d2d17e10866ae412332bb1a8a417b7 (patch) | |
| tree | b9c57ffcba9b81eb2d7a09af365e379e88aef47c /src/mainboard/intel/adlrvp/chromeos.c | |
| parent | 0f044a50074d50dea18a73ffd2683b3860c205e2 (diff) | |
mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot
List of changes:
1. Enable Root Port 8 aka 0:0x1c:7
2. Assign free running clock for RP8
3. Apply W/A to get card detected on x1 slot
- Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low
TEST=Able to detect PCIe SD card over x1 slot
localhost ~ # dmesg | grep mmc
[ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA
[ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8
[ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB
[ 3.849158] mmcblk0: p1
Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/chromeos.c')
0 files changed, 0 insertions, 0 deletions