mb/intel/adlrvp: Add ADL-P romstage mainboard code

List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD

TEST=Able to build and boot ADL-P RVP till ramstage early

Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 17 insertions, 0 deletions

diff --git a/src/mainboard/intel/adlrvp/board_id.h b/src/mainboard/intel/adlrvp/board_id.h
new file mode 100644
index 0000000000..2988127e9b
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/board_id.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
+#define _MAINBOARD_COMMON_BOARD_ID_H_
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD	0x0d
+/* Bit 5:0 for Board ID */
+#define BOARD_ID_MASK	0x3f
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */