mb/intel/adlrvp: Add ADL-P romstage mainboard code

List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD

TEST=Able to build and boot ADL-P RVP till ramstage early

Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 36 insertions, 0 deletions

diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c
new file mode 100644
index 0000000000..332ba1b7ae
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/board_id.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <ec/acpi/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <stdint.h>
+#include <types.h>
+#include "board_id.h"
+
+static uint32_t get_board_id_via_ext_ec(void)
+{
+	uint32_t id = BOARD_ID_INIT;
+
+	if (google_chromeec_get_board_version(&id))
+		id = BOARD_ID_UNKNOWN;
+
+	return id;
+}
+
+/* Get Board ID via EC I/O port write/read */
+int get_board_id(void)
+{
+	MAYBE_STATIC_NONZERO int id = -1;
+
+	if (id < 0) {
+		if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+			id = get_board_id_via_ext_ec();
+		} else {
+			if (send_ec_command(EC_FAB_ID_CMD) == 0) {
+				id = recv_ec_data() << 8;
+				id |= recv_ec_data();
+			}
+		}
+	}
+	return (id & BOARD_ID_MASK);
+}