diff options
| author | Usha P <usha.p@intel.com> | 2021-12-07 06:56:42 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2021-12-24 05:58:21 +0000 |
| commit | 112fde01abdc34887eee98a1bf2e406b5f2f3df2 (patch) | |
| tree | 4564df25a79e2fbb3f72e0dcebbae3ab404289f5 /src/mainboard/intel/adlrvp/Makefile.inc | |
| parent | 1d3cff3f612bf630b7d0040deba9b1a5df20c013 (diff) | |
mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
List of changes:
1. Add separate file for ADL-N GPIOs
2. Configure GPIOs as per the schematics of ADL-N RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/Makefile.inc')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 04c16455e8..0b658e5caa 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -7,6 +7,9 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y) bootblock-y += early_gpio_m.c ramstage-y += gpio_m.c +else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) +bootblock-y += early_gpio_n.c +ramstage-y += gpio_n.c else bootblock-y += early_gpio.c ramstage-y += gpio.c |