diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-06 20:13:06 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-11 14:15:49 +0000 |
| commit | 16e410669a369c4f09560cff99787e5439cd5e50 (patch) | |
| tree | c097527a5ee726d561347a9050b595d1f338936b /src/mainboard/intel/adlrvp/Makefile.inc | |
| parent | fb623a02c5a4d2258afef9b7c9fa7f2166ee0428 (diff) | |
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/Makefile.inc')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index eb4a9814df..e8a0eca790 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -1,11 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-only +subdirs-y += spd + bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c |