mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'

List of changes:
1. Use devicetree.cb from default location
2. Create variant directory for ADL RVP with external EC as
'adlrvp_p_ext_ec'
3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec'
to override 'devicetree.cb' as applicable.
4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec'
to mainboard directory

TEST=Build and boot both ADLRVP with onboard and external EC.

Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 4 insertions, 2 deletions

diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index 2ca32f3760..de924067d1 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -4,12 +4,14 @@ subdirs-y += spd
 
 bootblock-y += bootblock.c
 bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+bootblock-y += early_gpio.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += romstage_fsp_params.c
 romstage-y += board_id.c
+romstage-y += memory.c
 
 smm-y += smihandler.c
 
@@ -17,8 +19,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-y += mainboard.c
 ramstage-y += board_id.c
+ramstage-y += gpio.c
 
-subdirs-y += variants/baseboard
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 subdirs-y += variants/$(VARIANT_DIR)