diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2022-07-19 13:50:41 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-09 10:43:01 +0000 |
| commit | 323bddb1bdf53e5b871339868272cd7324856262 (patch) | |
| tree | a8432cda3d379f521fb9a9418b8118430bae9099 /src/mainboard/intel/adlrvp/Kconfig | |
| parent | 8754965db1d308a4e66e63fc85e39710f18f7f92 (diff) | |
mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl
Configure GPIO pins, add Kconfig options and enable
TPM device in devicetree.
Add H1 TPM IRQ GPIO pin in gpio.c
BUG=none
BRANCH=firmware-brya-14505.B
Cq-Depend: chromium:3774914
TEST=Boot the image and check the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/Kconfig')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Kconfig | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 987eeca3f0..1117bddfe0 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -40,6 +40,9 @@ config BOARD_INTEL_ADLRVP_RPL_EXT_EC select SOC_INTEL_ALDERLAKE_PCH_P select GEN3_EXTERNAL_CLOCK_BUFFER select DRIVERS_WWAN_FM350GL + select MAINBOARD_HAS_TPM2 + select SPI_TPM + select TPM_GOOGLE_CR50 config BOARD_INTEL_ADLRVP_P_MCHP select BOARD_INTEL_ADLRVP_COMMON @@ -167,7 +170,7 @@ endchoice config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC + select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC @@ -176,14 +179,14 @@ config UART_FOR_CONSOLE default 0 config DRIVER_TPM_SPI_BUS - default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC + default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC config USE_PM_ACPI_TIMER default n if BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_N config TPM_TIS_ACPI_INTERRUPT int - default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3) + default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3) config GEN3_EXTERNAL_CLOCK_BUFFER bool |