This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)

is based on amd-lx800/cs5536.

Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 148 insertions, 0 deletions

diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
new file mode 100644
index 0000000000..7c89aaffca
--- /dev/null
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
@@ -0,0 +1,148 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+	default ROM_SECTION_SIZE   = (ROM_SIZE - FALLBACK_SIZE)
+	default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE
+	object irq_tables.o
+end
+if USE_DCACHE_RAM
+	# Compile cache_as_ram.c to auto.inc.
+	makerule ./cache_as_ram_auto.inc
+			# depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			depends "$(MAINBOARD)/cache_as_ram_auto.c"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+	end
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+#	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+if USE_DCACHE_RAM
+	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
+	mainboardinit ./cache_as_ram_auto.inc
+end
+dir /pc80
+config chip.h
+
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end				# Northbridge
+		device pci 1.1 on end				# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+			register "lpc_serirq_enable" = "0x000010da"
+			register "lpc_serirq_polarity" = "0x0000EF25"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "1"	# 0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci 9.0 on end			# Slot1
+			device pci a.0 on end			# Slot2
+			device pci b.0 on end			# Slot3
+			device pci c.0 on end			# Slot4
+			device pci e.0 on end			# Ethernet 0
+			device pci 10.0 on end			# Ethernet 1
+			device pci 11.0 on end			# SATA
+			device pci f.0 on			# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off	# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on	# Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on	# Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end	# CIR
+					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
+					device pnp 2e.8 off end	# GPIO2
+					device pnp 2e.9 off end	# GPIO3
+					device pnp 2e.a off end	# ACPI
+					device pnp 2e.b off end	# HW Monitor
+				end
+			end
+			device pci f.2 on end			# IDE Controller
+			device pci f.3 on end			# Audio
+			device pci f.4 on end			# OHCI
+			device pci f.5 on end			# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+