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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-02-07 21:43:48 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-02-07 21:43:48 +0000
commitabf2ad716daff751d75907d47bcae4a7044fd7b4 (patch)
treef82427b43d76a4791253373affed1af8669e2e7b /src/mainboard/iei/juki-511p
parent389240f288b2708617a35ebe8d7f89b3bff316c5 (diff)
newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iei/juki-511p')
-rw-r--r--src/mainboard/iei/juki-511p/Config.lb157
-rw-r--r--src/mainboard/iei/juki-511p/Options.lb145
2 files changed, 0 insertions, 302 deletions
diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb
deleted file mode 100644
index c87ea5c70e..0000000000
--- a/src/mainboard/iei/juki-511p/Config.lb
+++ /dev/null
@@ -1,157 +0,0 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-default CONFIG_ROM_SIZE = 256 * 1024
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
-##
-default CONFIG_XIP_ROM_SIZE=65536
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-mainboardinit cpu/x86/16bit/reset16.inc
-ldscript /cpu/x86/16bit/reset16.lds
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files
-##
-#dir /pc80
-#config chip.h
-
-chip northbridge/amd/gx1
- device pci_domain 0 on
- device pci 0.0 on end
- chip southbridge/amd/cs5530
-
- device pci 12.0 on
- chip superio/winbond/w83977f
- device pnp 3f0.0 on # FDC
- irq 0x70 = 6
- end
- device pnp 3f0.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 3f0.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- register "com1" = "{115200}"
- device pnp 3f0.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- register "com2" = "{115200}"
- device pnp 3f0.4 on # RTC
- io 0x60 = 0x070
- irq 0x70 = 8
- end
- device pnp 3f0.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # Int 1 for PS/2 keyboard
- irq 0x72 = 12 # Int 12 for PS/2 mouse
- end
- device pnp 3f0.6 off # IR
- end
- device pnp 3f0.7 off # GPIO1
- end
- device pnp 3f0.8 off # GPIO
- end
- end
- device pci 12.1 on end # SMI
- device pci 12.2 on end # IDE
- device pci 12.3 on end # Audio
- device pci 12.4 on end # VGA onboard
-
- end
-
- device pci 0e.0 on end # ETH0
- device pci 13.0 on end # USB
-
- end
- end
-
- chip cpu/amd/model_gx1
- end
-
-end
-
diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb
deleted file mode 100644
index d7fde57fd0..0000000000
--- a/src/mainboard/iei/juki-511p/Options.lb
+++ /dev/null
@@ -1,145 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_UDELAY_IO
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-default CONFIG_UDELAY_IO=1
-##
-## Build code to export a programmable irq routing table
-##
-# FIXME: There's an irq_tables.c file, but CONFIG_GENERATE_PIRQ_TABLE is 0.
-default CONFIG_GENERATE_PIRQ_TABLE=0
-default CONFIG_IRQ_SLOT_COUNT=2
-default CONFIG_PIRQ_ROUTE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-default CONFIG_VIDEO_MB = 0
-
-end